(1) Field of the Invention
The present invention relates to a memory control apparatus which allows a plurality of masters to share data on an external memory and performs data transfer between the respective masters and the external memory.
(2) Description of the Related Art
In order to efficiently read out data on an external memory, the following techniques have been conventionally used: preparing a data buffer for the unit of access of the external memory side and reading out, in advance, data corresponding to the data buffer unit from the external memory and storing the data in the buffer in the case where a unit of access of an interface which accesses the external memory is larger than a unit of access of a master in a memory control apparatus; and reading out data from the data buffer without accessing the external memory in the case where read accesses to a unit address area occur in series. Here, when a specific master reads out the data, on the external memory, which has been rewritten by another master, the data buffer needs to be disabled because the data buffer is not always consistent with the external memory.
The following technique discloses: regarding, as a specific address, one of the addresses in a data buffer (for example, a start address or an end address of each data block of, for example, 16 bytes), and when it is detected that the master has read out data on the specific address, allowing a buffer control apparatus to disable the data buffer and read out data corresponding to a unit of access from the external memory in parallel, in order to reduce the number of accesses of the master by this disabling access (refer to Patent Reference 1: Japanese Patent Application Publication No. 6-243037, page 6 and FIG. 1).
In the case where a master of the apparatus disclosed in the above-described Publication accesses, at random, a specific address which is one of the addresses in a data buffer, the data buffer is always disabled at the time when the specific address is read out. This causes a problem that a hit rate of data in the data buffer becomes low, and thus the access efficiency to the external memory deteriorates.
In addition, a conventionally-performed approach in the case where the data buffer needs to be disabled is issuing an access request, as a dummy access request, for another address area on the external memory. This causes a problem that useless access time is required for issuing the access request to the external memory.
In addition, in a comparatively simple system which does not perform any exclusive control between the masters, an identical address is repeatedly read out, repeating a hit of data in a buffer when a specific master repeatedly makes a polling access to the specific address in order to detect whether the status of a system on the external memory has been rewritten by another master. This causes a problem that the data buffer becomes inconsistent with the external memory. However, the above-described Publication does not disclose the means to solve these problems.